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[/] [spi_master_slave/] [trunk/] [syn/] [ATLYS_02.SET] - Rev 10

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10 v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.
jdoin 3354d 11h /spi_master_slave/trunk/syn/ATLYS_02.SET

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