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[/] [spi_master_slave/] [trunk/] [syn/] [readme.txt] - Rev 9

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9 Updated verification data. jdoin 4899d 19h /spi_master_slave/trunk/syn/readme.txt
7 Updated code comments in VHDL files, added readme.txt files, updated work-in-progress version of the .doc core specification manual. jdoin 4900d 09h /spi_master_slave/trunk/syn/readme.txt
6 v1.10.0075: Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 4902d 06h /spi_master_slave/trunk/syn/readme.txt
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 4902d 06h /spi_master_slave/trunk/syn/readme.txt

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