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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys.ucf] - Rev 24

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24 - fixed range of the switch debouncer for the verification circuit
- reorganized rtl folder in mainstream trunk
jdoin 3328d 10h /spi_master_slave/trunk/syn/spi_master_atlys.ucf
22 spi_slave.vhd: v2.02.0126 [JD]
ISSUE: the miso_o MUX that preloads tx_bit when SSEL='1' will glitch for CPHA='1'.
FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update.
jdoin 3350d 01h /spi_master_slave/trunk/syn/spi_master_atlys.ucf
20 - removed folder trunk/bench.
- added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores.
jdoin 3368d 03h /spi_master_slave/trunk/syn/spi_master_atlys.ucf
12 SPI_SLAVE: v2.00.0110 [JD] FIX: CPHA bugs:
-- - redesigned core clocking to address all CPOL and CPHA configurations.
-- - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite
-- clock phases from SHIFT_EDGE.
-- Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
-- for each state, to avoid reported inference problems in some synthesis engines.
-- Streamlined port names and indentation blocks.
jdoin 3381d 00h /spi_master_slave/trunk/syn/spi_master_atlys.ucf
10 v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.
jdoin 3393d 00h /spi_master_slave/trunk/syn/spi_master_atlys.ucf
5 Changed clocking to use a single high-speed clock for the whole core, using clock enables to control slower timing.
Added SPI line clock divider from high-speed system clock.
Added pipeline delay logic to sync phase of SCK and MOSI, enabling very high operating frequencies.
Verified in silicon for SCK and MOSI at 50MHz, with very robust operation.
jdoin 3398d 23h /spi_master_slave/trunk/syn/spi_master_atlys.ucf

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