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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top_map.map] - Rev 24

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24 - fixed range of the switch debouncer for the verification circuit
- reorganized rtl folder in mainstream trunk
jdoin 3245d 16h /spi_master_slave/trunk/syn/spi_master_atlys_top_map.map
22 spi_slave.vhd: v2.02.0126 [JD]
ISSUE: the miso_o MUX that preloads tx_bit when SSEL='1' will glitch for CPHA='1'.
FIX: added a registered drive for the MUX select that will transfer the tx_reg only after the first tx_reg update.
jdoin 3267d 08h /spi_master_slave/trunk/syn/spi_master_atlys_top_map.map
20 - removed folder trunk/bench.
- added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores.
jdoin 3285d 09h /spi_master_slave/trunk/syn/spi_master_atlys_top_map.map

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