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Rev Log message Author Age Path
27 added test for CRC dkoethe 5913d 00h /
26 Initial Release dkoethe 5913d 00h /
25 added
> vcom -93 ../../../../../rtl/vhdl/PCK_CRC8_D8.vhd
> vcom -93 ../../../../../rtl/vhdl/PCK_CRC32_D32.vhd
> vcom -93 ../../../../../rtl/vhdl/crc_gen.vhd
> vcom -93 ../../../../../rtl/vhdl/crc_core.vhd
dkoethe 5913d 00h /
24 added Register C_ADR_RX_CRC. C_ADR_TX_CRC dkoethe 5913d 00h /
23 added logic for CRC-Generation dkoethe 5913d 00h /
22 added signal opb_m_last_block for CRC dkoethe 5913d 00h /
21 added constant C_ADR_RX_CRC,C_ADR_TX_CRC,
added constant C_OPB_CTL_REG_CRC_EN, C_OPB_CTL_REG_CRC_CLR
dkoethe 5913d 00h /
20 Initial Release dkoethe 5913d 00h /
19 Version 1.2 removed delays for simulation dkoethe 6017d 23h /
18 Version 1.1
Bugfix
added syncronisation registers opb_fifo_flg_int_r[0,1] to prevent metastability
dkoethe 6017d 23h /
17 no message dkoethe 6024d 20h /
16 no message dkoethe 6024d 23h /
15 increased C_NUM_FLG to 16, C_NUM_INT to 11 for opb_abort_flg dkoethe 6024d 23h /
14 - Added opb_abort_flg to component an Instance opb_m_if
- opb_irq_flg(10) <= opb_abort_flg;
- opb_fifo_flg(15 <= opb_fifo_flg;
dkoethe 6024d 23h /
13 Added opb_abort_flg to indicate a transfer failure dkoethe 6024d 23h /
12 Initial Release dkoethe 6027d 23h /
11 Changed Width of TX_DMA_NUM/RX_DMA_NUM from 16 to 24Bit to increase
maximal DMA-Transfer Size from 1 MByte to 256MByte
dkoethe 6029d 22h /
10 Changed opb_tx_dma_num, opb_rx_dma_num from fixed width of 16 to constant
C_WIDTH_DMA_NUM in opb_spi_slave_pack.vhd. Default Value: 24
dkoethe 6029d 22h /
9 Initial Release vhdldoc-Documentation dkoethe 6035d 21h /
8 no message dkoethe 6035d 21h /

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