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URL https://opencores.org/ocsvn/spi_slave/spi_slave/trunk

Subversion Repositories spi_slave

[/] [spi_slave/] [trunk/] - Rev 38

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Rev Log message Author Age Path
38 dkoethe 5533d 01h /spi_slave/trunk/
35 New directory structure. root 5535d 13h /spi_slave/trunk/
34 changed test TX-CRC Block from end of block to start
change crc value eb99fa90 to e4ea78bf		 dkoethe 5834d 03h /trunk/
33 moved TX CRC Value from end of packet to the start. dkoethe 5834d 03h /trunk/
32 added:
> lib opb_spi_slave_v1_00_a PCK_CRC32_D32.vhd vhdl
> lib opb_spi_slave_v1_00_a crc_gen.vhd vhdl
> lib opb_spi_slave_v1_00_a opb_spi_slave vhdl		 dkoethe 5834d 05h /trunk/
31 added PARAMETER C_CRC_EN = true, DT = BOOLEAN dkoethe 5834d 05h /trunk/
30 added doxygen comments dkoethe 5834d 05h /trunk/
29 Changed TX CRC-Calculation dkoethe 5834d 05h /trunk/
28 Changed TX CRC-Insertion dkoethe 5834d 05h /trunk/
27 added test for CRC dkoethe 5886d 03h /trunk/
26 Initial Release dkoethe 5886d 03h /trunk/
25 added
> vcom -93 ../../../../../rtl/vhdl/PCK_CRC8_D8.vhd
> vcom -93 ../../../../../rtl/vhdl/PCK_CRC32_D32.vhd
> vcom -93 ../../../../../rtl/vhdl/crc_gen.vhd
> vcom -93 ../../../../../rtl/vhdl/crc_core.vhd		 dkoethe 5886d 03h /trunk/
24 added Register C_ADR_RX_CRC. C_ADR_TX_CRC dkoethe 5886d 03h /trunk/
23 added logic for CRC-Generation dkoethe 5886d 03h /trunk/
22 added signal opb_m_last_block for CRC dkoethe 5886d 03h /trunk/
21 added constant C_ADR_RX_CRC,C_ADR_TX_CRC,
added constant C_OPB_CTL_REG_CRC_EN, C_OPB_CTL_REG_CRC_CLR		 dkoethe 5886d 03h /trunk/
20 Initial Release dkoethe 5886d 03h /trunk/
19 Version 1.2 removed delays for simulation dkoethe 5991d 02h /trunk/
18 Version 1.1
Bugfix
added syncronisation registers opb_fifo_flg_int_r[0,1] to prevent metastability		 dkoethe 5991d 02h /trunk/
17 no message dkoethe 5997d 23h /trunk/
16 no message dkoethe 5998d 02h /trunk/
15 increased C_NUM_FLG to 16, C_NUM_INT to 11 for opb_abort_flg dkoethe 5998d 03h /trunk/
14 - Added opb_abort_flg to component an Instance opb_m_if
- opb_irq_flg(10) <= opb_abort_flg;
- opb_fifo_flg(15 <= opb_fifo_flg;		 dkoethe 5998d 03h /trunk/
13 Added opb_abort_flg to indicate a transfer failure dkoethe 5998d 03h /trunk/
12 Initial Release dkoethe 6001d 03h /trunk/
11 Changed Width of TX_DMA_NUM/RX_DMA_NUM from 16 to 24Bit to increase
maximal DMA-Transfer Size from 1 MByte to 256MByte		 dkoethe 6003d 01h /trunk/
10 Changed opb_tx_dma_num, opb_rx_dma_num from fixed width of 16 to constant
C_WIDTH_DMA_NUM in opb_spi_slave_pack.vhd. Default Value: 24		 dkoethe 6003d 01h /trunk/
9 Initial Release vhdldoc-Documentation dkoethe 6009d 00h /trunk/
8 no message dkoethe 6009d 00h /trunk/
7 2007-11-22
added DMA-Registers and Register Description
removed Signal and Generic-Table for vhdl units. See vhdldoc HTML Documentation.		 dkoethe 6009d 00h /trunk/

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