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[/] [spi_slave/] [trunk/] [pcore/] - Rev 38

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Rev Log message Author Age Path
38 dkoethe 5531d 07h /spi_slave/trunk/pcore/
35 New directory structure. root 5533d 19h /spi_slave/trunk/pcore/
33 moved TX CRC Value from end of packet to the start. dkoethe 5832d 09h /trunk/pcore/
32 added:
> lib opb_spi_slave_v1_00_a PCK_CRC32_D32.vhd vhdl
> lib opb_spi_slave_v1_00_a crc_gen.vhd vhdl
> lib opb_spi_slave_v1_00_a opb_spi_slave vhdl		 dkoethe 5832d 10h /trunk/pcore/
31 added PARAMETER C_CRC_EN = true, DT = BOOLEAN dkoethe 5832d 10h /trunk/pcore/
30 added doxygen comments dkoethe 5832d 10h /trunk/pcore/
29 Changed TX CRC-Calculation dkoethe 5832d 10h /trunk/pcore/
28 Changed TX CRC-Insertion dkoethe 5832d 10h /trunk/pcore/
24 added Register C_ADR_RX_CRC. C_ADR_TX_CRC dkoethe 5884d 09h /trunk/pcore/
23 added logic for CRC-Generation dkoethe 5884d 09h /trunk/pcore/
22 added signal opb_m_last_block for CRC dkoethe 5884d 09h /trunk/pcore/
21 added constant C_ADR_RX_CRC,C_ADR_TX_CRC,
added constant C_OPB_CTL_REG_CRC_EN, C_OPB_CTL_REG_CRC_CLR		 dkoethe 5884d 09h /trunk/pcore/
20 Initial Release dkoethe 5884d 09h /trunk/pcore/
19 Version 1.2 removed delays for simulation dkoethe 5989d 08h /trunk/pcore/
18 Version 1.1
Bugfix
added syncronisation registers opb_fifo_flg_int_r[0,1] to prevent metastability		 dkoethe 5989d 08h /trunk/pcore/
16 no message dkoethe 5996d 08h /trunk/pcore/
15 increased C_NUM_FLG to 16, C_NUM_INT to 11 for opb_abort_flg dkoethe 5996d 08h /trunk/pcore/
14 - Added opb_abort_flg to component an Instance opb_m_if
- opb_irq_flg(10) <= opb_abort_flg;
- opb_fifo_flg(15 <= opb_fifo_flg;		 dkoethe 5996d 08h /trunk/pcore/
13 Added opb_abort_flg to indicate a transfer failure dkoethe 5996d 08h /trunk/pcore/
10 Changed opb_tx_dma_num, opb_rx_dma_num from fixed width of 16 to constant
C_WIDTH_DMA_NUM in opb_spi_slave_pack.vhd. Default Value: 24		 dkoethe 6001d 07h /trunk/pcore/

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