URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] - Rev 14

Rev	Log message	Author	Age	Path
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5246d 22h	/srdydrdy_lib/
13	Fixed FIFO Full condition for large fifo, added separate tests to example bridge	ghutchis	5250d 08h	/srdydrdy_lib/
12	Added absolute priority arbitration to ring to avoid having two ring taps transmit at same time	ghutchis	5251d 08h	/srdydrdy_lib/
11	Updated bridge example to fix a number of small bugs. First packet now exits bridge from all ports.	ghutchis	5252d 07h	/srdydrdy_lib/
10	Fixed "locked" variable in rrslow	ghutchis	5252d 11h	/srdydrdy_lib/
9	Added rx_gigmac, additional debug work on concentrator & fib	ghutchis	5252d 11h	/srdydrdy_lib/
8	Added compiling version of bridge example	ghutchis	5254d 00h	/srdydrdy_lib/
7	Added rrslow	ghutchis	5256d 03h	/srdydrdy_lib/
6	Modified "B" output buffer for full-rate operation	ghutchis	5258d 12h	/srdydrdy_lib/
5	Added new component for port ring	ghutchis	5259d 04h	/srdydrdy_lib/
4	Added example directory with basic bridge	ghutchis	5259d 22h	/srdydrdy_lib/
3	Added small/synchronizer FIFO, along with minimal testbench	ghutchis	5260d 22h	/srdydrdy_lib/
2	Initial commit of directory structure and basic components	ghutchis	5265d 07h	/srdydrdy_lib/
1	The project and the structure was created	root	5272d 23h	/srdydrdy_lib/