URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_head_b.v] - Rev 14

Rev	Log message	Author	Age	Path
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5235d 20h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_head_b.v
13	Fixed FIFO Full condition for large fifo, added separate tests to example bridge	ghutchis	5239d 07h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_head_b.v
6	Modified "B" output buffer for full-rate operation	ghutchis	5247d 10h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_head_b.v
2	Initial commit of directory structure and basic components	ghutchis	5254d 05h	/srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_head_b.v