URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

[/] - Rev 32

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Rev	Log message	Author	Age	Path
32	- bug-fix of block transfer operations => now fully ARM-compatible	zero_gravity	4437d 02h	/
31	- small documentary edits - CACHE.vhd modified for better synthesis results - BUS_UNIT.vhd update to fulfill WB specs	zero_gravity	4439d 13h	/
30	- minor edits in doc	zero_gravity	4444d 13h	/
29	- specific IO area is now auto protected - Wishbone compatibility extended - cache flush optimized - accelerated bus cycles due to less overhead	zero_gravity	4445d 14h	/
28	- bugfix in pipeline re-sync of d/i-cache - optimized bus unit - minor edits... ^^	zero_gravity	4456d 16h	/
27	updated "sim" folder - error in testbench environment -> old components -> weren't compatible to new core version anymore => FIXED! ;) - thanks to Pratip Mukherjee	zero_gravity	4460d 15h	/
26	bug fixes: - change in priority for cache miss/dirty/io_access - memory based pc modifications - removed internal timer	zero_gravity	4461d 16h	/
25	bug-fix in cache component: -> error in cache page-access history manager	zero_gravity	4469d 23h	/
24	- changed back to original oc svn folder structure - bug-fix in documentary - WB_ERR_I signal added to terminate wishbone bus access - bug-fix: system mode register set and privs	zero_gravity	4470d 22h	/
23		zero_gravity	4470d 23h	/
22	changed back to original svn folder structure	zero_gravity	4470d 23h	/
21	smaller, faster, better ;) * bug-fix: load-multiple instructions * new cache-control system * direct-accessible IO area can be specified * extended demo implementation	zero_gravity	4477d 18h	/
20	- update of data sheet -> note for system memory map layout and d-cache configuration	zero_gravity	4493d 12h	/
19	- simulation test bench added - example for compatible wishbone fabric/SoC added - block transfers from user bank updated	zero_gravity	4493d 16h	/
18	makefile update to ensure no thumb code is generated	zero_gravity	4498d 21h	/
17	small synthesis-friendly update of memory components	zero_gravity	4501d 14h	/
16	WB_TGC(5) signal fixed (indicating instruction/data fetch), coprocessor read-access bug fixed	zero_gravity	4501d 16h	/
15	new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;)	zero_gravity	4501d 21h	/
14	- corrected stupid error in access arbiter - updated minor issues	zero_gravity	4639d 17h	/
13	- corrected endianess converter for memory access - corrected error in temporal dependence detector	zero_gravity	4640d 13h	/

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Subversion Repositories storm_core

[/] - Rev 32

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