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Rev Log message Author Age Path
61 Added old uploaded documents to new repository. root 5531d 21h /
60 Added old uploaded documents to new repository. root 5532d 03h /
59 New directory structure. root 5532d 03h /
58 removed safe_switch from module (not needed) samg 8174d 20h /
57 removed saf_switch from int_cont module samg 8174d 20h /
56 rewrite with one less interface signal and simplification of verilog code samg 8174d 20h /
55 simplified regf_status interface samg 8174d 20h /
54 fixed case statement, sensitivity list samg 8177d 11h /
53 comment spelling fix samg 8177d 11h /
52 minor expression rewrite in 4th stage samg 8182d 20h /
51 Rewrote verilog for write enable signals for different destinations in the last stage.
The code is much easier to read and more liner to follow.		 samg 8183d 18h /
50 fixed sensitivity list error in last pipeline stage samg 8184d 07h /
49 changed run script name and added instructions samg 8184d 07h /
48 fixed neg edge event trigger samg 8184d 07h /
47 changed prefix from ~| to ! (same thing) samg 8184d 07h /
46 vcd dumpvar captures all levels samg 8186d 17h /
45 Fixed bug in 16 bit data swap instruction.
The instructions were making the regf status module look at reg 0
even though reg 0 didn't have anything to do with the purpose of
the instruction. Made reg b addr field mirror reg a field.
This error caused unecessary stalls.
Performance increase caused by calling instruction correctly and
not causing stalls from mal-formed instructions.		 samg 8186d 17h /
44 - Removed #1 delay (was originally put in for debug)
- Stall signal forced low during pipeline flush.
(No effect on functionality but it is easier to look at
the waveforms during debug)		 samg 8186d 18h /
43 integrated common rams into processor samg 8210d 12h /
42 minor header correction samg 8210d 12h /

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