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[/] [t48/] [tags/] [rel_0_2_beta/] - Rev 292

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292 New directory structure. root 5534d 17h /t48/tags/rel_0_2_beta/
252 This commit was manufactured by cvs2svn to create tag 'rel_0_2_beta'. 6505d 02h /tags/rel_0_2_beta/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7288d 15h /trunk/
112 update tb_behav_c0 for new ROM layout arniml 7288d 15h /trunk/
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7288d 15h /trunk/
110 exchange syn_rom for lpm_rom arniml 7288d 15h /trunk/
109 add new bug for release 0.1 BETA arniml 7289d 05h /trunk/
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7289d 05h /trunk/
107 tie EA to '1' arniml 7289d 05h /trunk/
106 clean-up use of ea_i arniml 7289d 05h /trunk/
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7291d 15h /trunk/
104 add white_box directory to test suite arniml 7292d 12h /trunk/
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7292d 12h /trunk/
102 update for changes in address space of external memory arniml 7292d 12h /trunk/
101 assert p2_read_p2_o when expander port is read arniml 7292d 12h /trunk/
100 reorder data_o generation arniml 7292d 12h /trunk/
99 initial check-in arniml 7292d 12h /trunk/
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7292d 13h /trunk/
97 initial check-in arniml 7292d 13h /trunk/
96 select dedicated directorie(s) for regression arniml 7293d 10h /trunk/

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