OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] - Rev 292

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
292 New directory structure. root 5534d 11h /t48/tags/rel_0_3_beta/
253 This commit was manufactured by cvs2svn to create tag 'rel_0_3_beta'. 6504d 19h /tags/rel_0_3_beta/
129 cleanup copyright notice arniml 7237d 04h /trunk/
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered
arniml 7244d 07h /trunk/
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge
arniml 7244d 08h /trunk/
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell
arniml 7244d 09h /trunk/
125 exclude from dump compare arniml 7244d 09h /trunk/
124 fix wrong handling of MB after return from interrupt arniml 7245d 06h /trunk/
123 support hex file for external ROM arniml 7245d 06h /trunk/
122 test MB after return from interrupt arniml 7245d 06h /trunk/
121 update bug description for
Program Memory bank can be switched during interrupt
arniml 7247d 23h /trunk/
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts
arniml 7247d 23h /trunk/
119 add int_in_progress_o to entity of int module arniml 7247d 23h /trunk/
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"
arniml 7247d 23h /trunk/
117 add bug
Program Memory bank can be switched during interrupt
arniml 7249d 00h /trunk/
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7277d 00h /trunk/
115 extend description arniml 7278d 04h /trunk/
114 initial check-in arniml 7282d 00h /trunk/
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM
arniml 7288d 09h /trunk/
112 update tb_behav_c0 for new ROM layout arniml 7288d 09h /trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.