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[/] [t48/] [tags/] [rel_0_6__beta/] - Rev 293

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Rev Log message Author Age Path
292 New directory structure. root 5550d 04h /t48/tags/rel_0_6__beta/
257 This commit was manufactured by cvs2svn to create tag 'rel_0_6__beta'. 6520d 13h /tags/rel_0_6__beta/
193 iManual arniml 6791d 05h /trunk/
192 update list for Wishbone toplevel arniml 6791d 16h /trunk/
191 preliminary version 0.2 arniml 6791d 20h /trunk/
190 finalize change log for release 0.6 beta arniml 6792d 14h /trunk/
189 add bug report
"Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"		 arniml 6823d 16h /trunk/
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6823d 16h /trunk/
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6823d 17h /trunk/
186 update to version 0.2 arniml 6824d 18h /trunk/
185 initial check-in arniml 6829d 16h /trunk/
184 initial check-in arniml 6829d 17h /trunk/
183 fix missing assignment to outclock arniml 6829d 20h /trunk/
182 intermediate version arniml 6909d 19h /trunk/
181 fix typo arniml 6909d 22h /trunk/
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6918d 03h /trunk/
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6918d 03h /trunk/
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 6919d 15h /trunk/
177 Implement db_dir_o glitch-safe arniml 6919d 15h /trunk/
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6919d 15h /trunk/

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