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Rev Log message Author Age Path
43 *** empty log message *** jesus 7846d 23h /
42 Fixed bus req/ack cycle jesus 7846d 23h /
41 Removed UNISIM library jesus 7846d 23h /
40 Cleanup jesus 7846d 23h /
39 Added -n option and component declaration jesus 7874d 21h /
38 Added Leonardo .ucf generation jesus 7874d 21h /
37 Changed to single register file jesus 7875d 00h /
36 Added component declaration jesus 7875d 00h /
35 Release 0242 jesus 7881d 12h /
34 Updated for ISE 5.1 jesus 7881d 17h /
33 Fixed typo jesus 7891d 09h /
32 Fixed for ISE 5.1 jesus 7891d 09h /
31 Fixed generic name error jesus 7894d 11h /
30 Changed to xilinx specific RAM jesus 7900d 10h /
29 Fixed (IX/IY+d) timing and added all GB op-codes jesus 7900d 10h /
28 Adapted for zxgate jesus 7901d 11h /
27 Xilinx SSRAM, initial release jesus 7901d 11h /
26 Fixed instruction timing for POP and DJNZ jesus 7915d 03h /
25 IX/IY timing and ADC/SBC fix jesus 7916d 12h /
24 no message jesus 7922d 09h /

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