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[/] - Rev 41

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21 The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. earlz 4378d 14h /
20 fuck it. All sorts of broken, will try to fix it tomorrow earlz 4379d 14h /
19 Got beginning of core/decoder for the CPU earlz 4379d 15h /
18 Finished memory controller earlz 4383d 01h /
17 Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct
earlz 4383d 15h /
16 Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.
earlz 4386d 17h /
15 Added README, LICENSE, and the (so far not created) incdec component earlz 4388d 14h /
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4388d 23h /
13 Forgot about the new library I added earlz 4389d 01h /
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD
earlz 4389d 02h /

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