URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [src/] [memory.vhd] - Rev 41

Rev	Log message	Author	Age	Path
41	Well, finally got ports to work properly without latches. Had to reimplement a specific more complex form of RAM basically. The code is horrid, but testcases pass	earlz	4367d 05h	/tinycpu/trunk/src/memory.vhd
38	Made it synthesize without latches	earlz	4370d 07h	/tinycpu/trunk/src/memory.vhd
37	Worked on the assembler more Added a memory mapped port to memory.vhd. This change causes a lot of latches to be inferred in synthesis however, so this will have to change some	earlz	4372d 05h	/tinycpu/trunk/src/memory.vhd
19	Got beginning of core/decoder for the CPU	earlz	4381d 06h	/tinycpu/trunk/src/memory.vhd
18	Finished memory controller	earlz	4384d 16h	/tinycpu/trunk/src/memory.vhd
7	Changed memory to fix bound check error Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)	earlz	4395d 15h	/tinycpu/trunk/src/memory.vhd
6	Reworked memory code to hopefully synthesize better	earlz	4395d 19h	/tinycpu/trunk/src/memory.vhd
4	Added internal memory interface Updated design	earlz	4396d 14h	/tinycpu/trunk/src/memory.vhd