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[/] [tinycpu/] [trunk/] [testbench/] [top_tb.vhd] - Rev 41

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41 Well, finally got ports to work properly without latches. Had to reimplement a specific more complex form of RAM basically. The code is horrid, but testcases pass earlz 4367d 11h /tinycpu/trunk/testbench/top_tb.vhd
40 Design doesn't pass synthesis right now. Not for sure why.
Fixed bug with encoding of second opcode byte in assembler
Added testcase for toggle program		 earlz 4369d 11h /tinycpu/trunk/testbench/top_tb.vhd
39 A lot of work in the assembler. It now supports nearly every opcode implemented and is a lot cleaner
Added a bootrom. There isn't really a point in testbenching this.. I'm not for sure how I would, and it will change so much in these early days that it'll be pointless I think
Everything should be ready to go for a test on actual hardware now!		 earlz 4370d 10h /tinycpu/trunk/testbench/top_tb.vhd
37 Worked on the assembler more
Added a memory mapped port to memory.vhd. This change causes a lot of latches to be inferred in synthesis however, so this will have to change some		 earlz 4372d 10h /tinycpu/trunk/testbench/top_tb.vhd
28 Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers		 earlz 4378d 13h /tinycpu/trunk/testbench/top_tb.vhd
25 Wait for memory state now works as expected, and opcode `mov [reg], immd` works now earlz 4379d 00h /tinycpu/trunk/testbench/top_tb.vhd
23 Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core		 earlz 4379d 18h /tinycpu/trunk/testbench/top_tb.vhd

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