URL https://opencores.org/ocsvn/ts7300_opencore/ts7300_opencore/trunk

Subversion Repositories ts7300_opencore

[/] - Rev 7

Rev	Log message	Author	Age	Path
7	Added old uploaded documents to new repository.	root	5531d 00h	/
6	Added old uploaded documents to new repository.	root	5531d 06h	/
5	New directory structure.	root	5531d 06h	/
4	Fix async set race condition and allow ethernet to be parameterizable so it can be left out.	joff	6320d 13h	/
3	Fix bus demultiplexer.	joff	6348d 20h	/
2	Initial import of ts7300_opencore. Quartus II project tree for Technologic Systems TS-7300 FPGA Linux Computer. Contains WISHBONE bridge verilog as well as pin locks, timing constraints, and various other Quartus II project metadata. Also included is a sample implementation of the open-ethernet core as well as a stub WISHBONE slave demonstrating a 32-bit register in the address space of the ARM9 CPU running Linux.	joff	6532d 15h	/
1	Standard project directories initialized by cvs2svn.		6532d 15h	/