URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

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Rev	Log message	Author	Age	Path
86	Added old uploaded documents to new repository.	root	5534d 06h	/
85	Added old uploaded documents to new repository.	root	5534d 12h	/
84	New directory structure.	root	5534d 12h	/
83	Some fixes from Guy-- replace case with casex.	hharte	5607d 18h	/
82	Clean up spacing	hharte	5617d 14h	/
81	Initial version of TV80 Wishbone Wrapper	hharte	5617d 15h	/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6717d 03h	/
79	Added JR self-checking test	ghutchis	6717d 03h	/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6760d 05h	/
77	Added back files lost after server crash	ghutchis	6791d 23h	/
76	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6871d 05h	/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6871d 05h	/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6871d 06h	/
73	Added RC4 encrypt/decrypt test	ghutchis	6883d 00h	/
72	Added copyright header	ghutchis	6883d 00h	/
71	Ported UART from T80	ghutchis	6944d 04h	/
70	Added test for T16450 UART	ghutchis	6994d 23h	/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	6994d 23h	/
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7003d 00h	/
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7003d 00h	/

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Subversion Repositories tv80

[/] - Rev 86

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