OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [asyst_2/] [rtl/] - Rev 106

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 New directory structure. root 5548d 22h /uart16550/tags/asyst_2/rtl/
76 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 8124d 15h /uart16550/tags/asyst_2/rtl/
75 Endian define added. Big Byte Endian is selected by default. mohor 8124d 15h /uart16550/tags/asyst_2/rtl/
74 tf_overrun signal was disabled since it was not used gorban 8129d 16h /uart16550/tags/asyst_2/rtl/
73 major bug in 32-bit mode that prevented register access fixed. gorban 8136d 16h /uart16550/tags/asyst_2/rtl/
71 Removed confusing comment gorban 8161d 12h /uart16550/tags/asyst_2/rtl/
70 tf_pop was too wide. Now it is only 1 clk cycle width. mohor 8166d 20h /uart16550/tags/asyst_2/rtl/
69 More than one character was stored in case of break. End of the break
was not detected correctly.
mohor 8175d 11h /uart16550/tags/asyst_2/rtl/
68 lsr[7] was not showing overrun errors. mohor 8178d 19h /uart16550/tags/asyst_2/rtl/
67 Missing declaration of rf_push_q fixed. mohor 8185d 18h /uart16550/tags/asyst_2/rtl/
66 rx push changed to be only one cycle wide. mohor 8185d 19h /uart16550/tags/asyst_2/rtl/
65 Warnings fixed (unused signals removed). mohor 8186d 23h /uart16550/tags/asyst_2/rtl/
64 Warnings cleared. mohor 8187d 00h /uart16550/tags/asyst_2/rtl/
63 Synplicity was having troubles with the comment. mohor 8187d 00h /uart16550/tags/asyst_2/rtl/
62 Bug that was entered in the last update fixed (rx state machine). mohor 8187d 23h /uart16550/tags/asyst_2/rtl/
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.
mohor 8188d 17h /uart16550/tags/asyst_2/rtl/
60 Things related to msr register changed. After THRE IRQ occurs, and one
character is written to the transmit fifo, the detection of the THRE bit in the
LSR is delayed for one character time.
mohor 8188d 22h /uart16550/tags/asyst_2/rtl/
59 MSR register fixed. mohor 8191d 19h /uart16550/tags/asyst_2/rtl/
58 After reset modem status register MSR should be reset. mohor 8191d 22h /uart16550/tags/asyst_2/rtl/
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).
mohor 8192d 21h /uart16550/tags/asyst_2/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.