OpenCores
URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_3/] - Rev 106

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 New directory structure. root 5535d 12h /uart16550/tags/rel_3/
102 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7289d 09h /tags/rel_3/
101 Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. tadejm 7289d 09h /trunk/
100 Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs. tadejm 7289d 10h /trunk/
99 Added synchronizer flops for RX input. tadejm 7289d 10h /trunk/
98 Added to synchronize RX input to Wishbone clock. tadejm 7289d 10h /trunk/
96 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This sauses testcases not to finish. tadejm 7344d 18h /trunk/
95 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish. tadejm 7344d 18h /trunk/
94 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7344d 18h /trunk/
93 Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish. tadejm 7344d 18h /trunk/
92 This is revision 1.4, revision 1.5 was put there by mistake. simons 7458d 11h /trunk/
91 Removed files due to new complete testbench. tadejm 7459d 02h /trunk/
90 Add Flextronics header avisha 7461d 09h /trunk/
89 adjusted comment + define dries 7541d 14h /trunk/
88 added clearing the receiver fifo statuses on resets gorban 7604d 04h /trunk/
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7634d 05h /trunk/
86 restored include for uart_defines.v in uart_test.v gorban 7904d 09h /trunk/
85 Updated documentation to include latest changes. gorban 7938d 01h /trunk/
84 The uart_defines.v file is included again in sources. gorban 7951d 01h /trunk/
83 Reverted to include uart_defines.v file in other files again. gorban 7951d 01h /trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.