URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] - Rev 106

Rev	Log message	Author	Age	Path
86	restored include for uart_defines.v in uart_test.v	gorban	7918d 17h	/
85	Updated documentation to include latest changes.	gorban	7952d 09h	/
84	The uart_defines.v file is included again in sources.	gorban	7965d 09h	/
83	Reverted to include uart_defines.v file in other files again.	gorban	7965d 09h	/
82	Updated to work with latest core.	gorban	7972d 07h	/
81	Added lastest additions.	gorban	7972d 07h	/
80	Remove uart_fifo.v because it is replaced by other 2 files.	gorban	7972d 07h	/
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	7972d 07h	/
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8125d 13h	/
77	This commit was manufactured by cvs2svn to create tag 'asyst_3'.		8125d 13h	/