URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] [uart16750/] [trunk/] - Rev 25

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Rev	Log message	Author	Age	Path
25	UART16750: Updated testbench	hasw	5026d 00h	/uart16750/trunk/
24	Inverted low active outputs when RST is active	hasw	5026d 00h	/uart16750/trunk/
23	Fixed paths in Makefile for simulation	hasw	5390d 03h	/uart16750/trunk/
22	Removed old stimuli data file, created by perl script	hasw	5390d 03h	/uart16750/trunk/
21	Updated simulation files	hasw	5390d 03h	/uart16750/trunk/
20	UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state	hasw	5520d 01h	/uart16750/trunk/
17	New directory structure.	root	5536d 11h	/uart16750/trunk/
16	UART16750: Added example project	hasw	5556d 22h	/trunk/
15	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5566d 01h	/trunk/
14	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5567d 03h	/trunk/
13	UART16750: Added automatic flow control	hasw	5580d 03h	/trunk/
12	UART16750: Updated stimuli script with automatic flow control tests	hasw	5580d 04h	/trunk/
11	UART16750: Removed dependency from std_logic_unsigned	hasw	5580d 04h	/trunk/
10	UART16750: Removed dependency from std_logic_unsigned	hasw	5580d 04h	/trunk/
9	Registered control line outputs	hasw	5589d 06h	/trunk/
8	Make memory read in generic FIFO model synchronous for optimized used with XST	hasw	5589d 06h	/trunk/
7	Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST	hasw	5590d 10h	/trunk/
6	THR empty interrupt register connected to RST	hasw	5590d 11h	/trunk/
5	Removed old component	hasw	5591d 05h	/trunk/
4	Removed swap file	hasw	5591d 06h	/trunk/

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Subversion Repositories uart16750

[/] [uart16750/] [trunk/] - Rev 25

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