OpenCores
URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] [uart16750/] [trunk/] [rtl/] [vhdl/] [uart_16750.vhd] - Rev 24

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 Inverted low active outputs when RST is active hasw 5047d 15h /uart16750/trunk/rtl/vhdl/uart_16750.vhd
17 New directory structure. root 5558d 01h /uart16750/trunk/rtl/vhdl/uart_16750.vhd
15 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5587d 15h /uart16750/trunk/rtl/vhdl/uart_16750.vhd
13 UART16750: Added automatic flow control hasw 5601d 18h /uart16750/trunk/rtl/vhdl/uart_16750.vhd
9 Registered control line outputs hasw 5610d 20h /uart16750/trunk/rtl/vhdl/uart_16750.vhd
6 THR empty interrupt register connected to RST hasw 5612d 01h /uart16750/trunk/rtl/vhdl/uart_16750.vhd
2 Imported sources hasw 5612d 21h /uart16750/trunk/rtl/vhdl/uart_16750.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.