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14 Adding simplified BSD license file motilito 2741d 10h /
13 VHDL version:
- Add GHDL support for automated testbenches.
- Migrate to ieee.numeric_std.
- Reorganize a little bit the test benches.
smuller 3075d 00h /
12 Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism. motilito 4531d 04h /
11 VHDL version:
- Add a request-grant mechanism. This will permit to use it on a shared bus without any bus contention.
- Improve the test benches.
- Automate the launching of test benches.
- Fix a bug in 'uartRx.vhd'.
- Reorganize a little bit the directory structure.
smuller 4532d 19h /
10 VHDL version: corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. smuller 4624d 17h /
9 Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. motilito 4626d 04h /
8 Updated core description document to include Lattice device synthesis results. motilito 4847d 09h /
7 Updated the Scilab script for Scilab 5.3 version. Previous versions might not work. motilito 4868d 18h /
6 Commit VHDL description source with basic test benches smuller 5118d 03h /
5 Add structure for VHDL (verilog similar tree). smuller 5129d 20h /
4 Corrected some problems in the binary mode protocol test bench.
Updated documentation.
motilito 5224d 18h /
3 motilito 5271d 01h /
2 Uploaded the initial project version. motilito 5271d 02h /
1 The project and the structure was created root 5273d 19h /

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