URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] - Rev 10

Rev	Log message	Author	Age	Path
10	VHDL version: corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	smuller	4683d 08h	/
9	Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	motilito	4684d 18h	/
8	Updated core description document to include Lattice device synthesis results.	motilito	4905d 23h	/
7	Updated the Scilab script for Scilab 5.3 version. Previous versions might not work.	motilito	4927d 08h	/
6	Commit VHDL description source with basic test benches	smuller	5176d 17h	/
5	Add structure for VHDL (verilog similar tree).	smuller	5188d 11h	/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5283d 09h	/
3		motilito	5329d 15h	/
2	Uploaded the initial project version.	motilito	5329d 16h	/
1	The project and the structure was created	root	5332d 10h	/