URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] - Rev 6

Rev	Log message	Author	Age	Path
6	Commit VHDL description source with basic test benches	smuller	5033d 00h	/uart2bus/
5	Add structure for VHDL (verilog similar tree).	smuller	5044d 17h	/uart2bus/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5139d 15h	/uart2bus/
3		motilito	5185d 21h	/uart2bus/
2	Uploaded the initial project version.	motilito	5185d 22h	/uart2bus/
1	The project and the structure was created	root	5188d 16h	/uart2bus/