URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] - Rev 7

Rev	Log message	Author	Age	Path
7	Updated the Scilab script for Scilab 5.3 version. Previous versions might not work.	motilito	4787d 21h	/uart2bus/
6	Commit VHDL description source with basic test benches	smuller	5037d 06h	/uart2bus/
5	Add structure for VHDL (verilog similar tree).	smuller	5049d 00h	/uart2bus/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5143d 22h	/uart2bus/
3		motilito	5190d 04h	/uart2bus/
2	Uploaded the initial project version.	motilito	5190d 05h	/uart2bus/
1	The project and the structure was created	root	5192d 23h	/uart2bus/