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[/] [uart2bus/] [trunk/] - Rev 14

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Rev Log message Author Age Path
14 Adding simplified BSD license file motilito 824d 22h /uart2bus/trunk/
13 VHDL version:
- Add GHDL support for automated testbenches.
- Migrate to ieee.numeric_std.
- Reorganize a little bit the test benches.
smuller 1158d 12h /uart2bus/trunk/
12 Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism. motilito 2614d 15h /uart2bus/trunk/
11 VHDL version:
- Add a request-grant mechanism. This will permit to use it on a shared bus without any bus contention.
- Improve the test benches.
- Automate the launching of test benches.
- Fix a bug in 'uartRx.vhd'.
- Reorganize a little bit the directory structure.
smuller 2616d 06h /uart2bus/trunk/
10 VHDL version: corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. smuller 2708d 05h /uart2bus/trunk/
9 Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. motilito 2709d 15h /uart2bus/trunk/
8 Updated core description document to include Lattice device synthesis results. motilito 2930d 20h /uart2bus/trunk/
7 Updated the Scilab script for Scilab 5.3 version. Previous versions might not work. motilito 2952d 05h /uart2bus/trunk/
6 Commit VHDL description source with basic test benches smuller 3201d 14h /uart2bus/trunk/
5 Add structure for VHDL (verilog similar tree). smuller 3213d 08h /uart2bus/trunk/
4 Corrected some problems in the binary mode protocol test bench.
Updated documentation.
motilito 3308d 06h /uart2bus/trunk/
3 motilito 3354d 12h /uart2bus/trunk/
2 Uploaded the initial project version. motilito 3354d 13h /uart2bus/trunk/
1 The project and the structure was created root 3357d 07h /uart2bus/trunk/

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