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[/] [uart2bus/] [trunk/] - Rev 12

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12 Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism. motilito 4608d 19h /uart2bus/trunk/
11 VHDL version:
- Add a request-grant mechanism. This will permit to use it on a shared bus without any bus contention.
- Improve the test benches.
- Automate the launching of test benches.
- Fix a bug in 'uartRx.vhd'.
- Reorganize a little bit the directory structure.
smuller 4610d 11h /uart2bus/trunk/
10 VHDL version: corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. smuller 4702d 09h /uart2bus/trunk/
9 Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. motilito 4703d 20h /uart2bus/trunk/
8 Updated core description document to include Lattice device synthesis results. motilito 4925d 00h /uart2bus/trunk/
7 Updated the Scilab script for Scilab 5.3 version. Previous versions might not work. motilito 4946d 09h /uart2bus/trunk/
6 Commit VHDL description source with basic test benches smuller 5195d 19h /uart2bus/trunk/
5 Add structure for VHDL (verilog similar tree). smuller 5207d 12h /uart2bus/trunk/
4 Corrected some problems in the binary mode protocol test bench.
Updated documentation.
motilito 5302d 10h /uart2bus/trunk/
3 motilito 5348d 16h /uart2bus/trunk/
2 Uploaded the initial project version. motilito 5348d 17h /uart2bus/trunk/
1 The project and the structure was created root 5351d 11h /uart2bus/trunk/

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