OpenCores
URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] - Rev 12

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
12 Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism. motilito 4605d 04h /uart2bus/trunk/verilog/
9 Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. motilito 4700d 05h /uart2bus/trunk/verilog/
4 Corrected some problems in the binary mode protocol test bench.
Updated documentation.
motilito 5298d 19h /uart2bus/trunk/verilog/
3 motilito 5345d 01h /uart2bus/trunk/verilog/
2 Uploaded the initial project version. motilito 5345d 03h /uart2bus/trunk/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.