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[/] [uart2bus/] [trunk/] [verilog/] [bench/] - Rev 12


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Rev Log message Author Age Path
12 Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism. motilito 4238d 20h /uart2bus/trunk/verilog/bench/
4 Corrected some problems in the binary mode protocol test bench.
Updated documentation.
motilito 4932d 10h /uart2bus/trunk/verilog/bench/
2 Uploaded the initial project version. motilito 4978d 18h /uart2bus/trunk/verilog/bench/

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