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[/] [uart2bus/] [trunk/] [verilog/] [bench/] [tb_uart2bus_top.v] - Rev 12

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12 Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism. motilito 4607d 08h /uart2bus/trunk/verilog/bench/tb_uart2bus_top.v
2 Uploaded the initial project version. motilito 5347d 07h /uart2bus/trunk/verilog/bench/tb_uart2bus_top.v

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