URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [rtl] - Rev 12

Rev	Log message	Author	Age	Path
12	Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.	motilito	4449d 21h	/uart2bus/trunk/verilog/rtl
9	Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	motilito	4544d 21h	/uart2bus/trunk/verilog/rtl
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5143d 12h	/uart2bus/trunk/verilog/rtl
3		motilito	5189d 18h	/uart2bus/trunk/verilog/rtl
2	Uploaded the initial project version.	motilito	5189d 19h	/uart2bus/trunk/verilog/rtl