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[/] [uart2bus] - Rev 14

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Rev Log message Author Age Path
14 Adding simplified BSD license file motilito 2662d 14h /uart2bus
13 VHDL version:
- Add GHDL support for automated testbenches.
- Migrate to ieee.numeric_std.
- Reorganize a little bit the test benches.		 smuller 2996d 03h /uart2bus
12 Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism. motilito 4452d 07h /uart2bus
11 VHDL version:
- Add a request-grant mechanism. This will permit to use it on a shared bus without any bus contention.
- Improve the test benches.
- Automate the launching of test benches.
- Fix a bug in 'uartRx.vhd'.
- Reorganize a little bit the directory structure.		 smuller 4453d 22h /uart2bus
10 VHDL version: corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. smuller 4545d 20h /uart2bus
9 Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. motilito 4547d 07h /uart2bus
8 Updated core description document to include Lattice device synthesis results. motilito 4768d 12h /uart2bus
7 Updated the Scilab script for Scilab 5.3 version. Previous versions might not work. motilito 4789d 21h /uart2bus
6 Commit VHDL description source with basic test benches smuller 5039d 06h /uart2bus
5 Add structure for VHDL (verilog similar tree). smuller 5051d 00h /uart2bus
4 Corrected some problems in the binary mode protocol test bench.
Updated documentation.		 motilito 5145d 22h /uart2bus
3 motilito 5192d 04h /uart2bus
2 Uploaded the initial project version. motilito 5192d 05h /uart2bus
1 The project and the structure was created root 5194d 23h /uart2bus

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