URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] - Rev 10

Rev	Log message	Author	Age	Path
10	add maximum simulation time + refine the reporting phase	HanySalah	2526d 04h	/uart2bus_testbench/trunk/tb/
9	Change the verbosity of passed test message to be UVM_HIGH + add the reporting message in the report phase in testfile	HanySalah	2526d 04h	/uart2bus_testbench/trunk/tb/
8		HanySalah	2655d 10h	/uart2bus_testbench/trunk/tb/
7	Remove run tests from topmodule	HanySalah	3014d 02h	/uart2bus_testbench/trunk/tb/
6		HanySalah	3014d 02h	/uart2bus_testbench/trunk/tb/
5	remove coverage requirement section	HanySalah	3014d 14h	/uart2bus_testbench/trunk/tb/
4		HanySalah	3014d 15h	/uart2bus_testbench/trunk/tb/
3		HanySalah	3014d 15h	/uart2bus_testbench/trunk/tb/
2	Initial Version	HanySalah	3040d 04h	/uart2bus_testbench/trunk/tb/