URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [test/] - Rev 10

Rev	Log message	Author	Age	Path
10	add maximum simulation time + refine the reporting phase	HanySalah	2522d 17h	/uart2bus_testbench/trunk/tb/test/
9	Change the verbosity of passed test message to be UVM_HIGH + add the reporting message in the report phase in testfile	HanySalah	2522d 18h	/uart2bus_testbench/trunk/tb/test/
8		HanySalah	2652d 00h	/uart2bus_testbench/trunk/tb/test/
3		HanySalah	3011d 04h	/uart2bus_testbench/trunk/tb/test/
2	Initial Version	HanySalah	3036d 18h	/uart2bus_testbench/trunk/tb/test/