URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] - Rev 29

Rev	Log message	Author	Age	Path
29	ACTEL syn define	unneback	5022d 13h	/versatile_fifo/
28	ACTEL async dual way FIFO	unneback	5029d 23h	/versatile_fifo/
27	initial commit, dual way simplex FIFO	unneback	5030d 14h	/versatile_fifo/
26	added ACTEL synthesis directive as define, +ACTEL	unneback	5030d 14h	/versatile_fifo/
25	DFF SR as separate logic	unneback	5170d 10h	/versatile_fifo/
24	updated fifo interfaces with re/rd and we/wr	unneback	5171d 00h	/versatile_fifo/
23		unneback	5173d 12h	/versatile_fifo/
22	async fifo with multiple queues	unneback	5173d 13h	/versatile_fifo/
21	added DFF SR	unneback	5187d 11h	/versatile_fifo/
20		unneback	5187d 18h	/versatile_fifo/
19	DFF with async clear and set for Altera cycloneIV	unneback	5189d 00h	/versatile_fifo/
18	ADDR and DATA width set to 8 resp 32	unneback	5189d 14h	/versatile_fifo/
17	based on updated versatile counter	unneback	5193d 12h	/versatile_fifo/
16	changed power of two style	unneback	5456d 22h	/versatile_fifo/
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5460d 16h	/versatile_fifo/
14	added PDF	unneback	5504d 22h	/versatile_fifo/
13	adr update	unneback	5506d 00h	/versatile_fifo/
12	no mux on dual port mem read	unneback	5518d 18h	/versatile_fifo/
11	name conflict wptr1 changed to wptr1_cnt etc	unneback	5518d 20h	/versatile_fifo/
10	rptr2	unneback	5518d 22h	/versatile_fifo/