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[/] [versatile_fifo/] - Rev 31

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Rev Log message Author Age Path
31 port map unneback 5013d 11h /versatile_fifo/
30 port map unneback 5013d 12h /versatile_fifo/
29 ACTEL syn define unneback 5021d 09h /versatile_fifo/
28 ACTEL async dual way FIFO unneback 5028d 18h /versatile_fifo/
27 initial commit, dual way simplex FIFO unneback 5029d 10h /versatile_fifo/
26 added ACTEL synthesis directive as define, +ACTEL unneback 5029d 10h /versatile_fifo/
25 DFF SR as separate logic unneback 5169d 06h /versatile_fifo/
24 updated fifo interfaces with re/rd and we/wr unneback 5169d 20h /versatile_fifo/
23 unneback 5172d 08h /versatile_fifo/
22 async fifo with multiple queues unneback 5172d 09h /versatile_fifo/
21 added DFF SR unneback 5186d 07h /versatile_fifo/
20 unneback 5186d 14h /versatile_fifo/
19 DFF with async clear and set for Altera cycloneIV unneback 5187d 20h /versatile_fifo/
18 ADDR and DATA width set to 8 resp 32 unneback 5188d 10h /versatile_fifo/
17 based on updated versatile counter unneback 5192d 08h /versatile_fifo/
16 changed power of two style unneback 5455d 18h /versatile_fifo/
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5459d 12h /versatile_fifo/
14 added PDF unneback 5503d 18h /versatile_fifo/
13 adr update unneback 5504d 20h /versatile_fifo/
12 no mux on dual port mem read unneback 5517d 14h /versatile_fifo/

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