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[/] [versatile_fifo/] - Rev 32

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Rev Log message Author Age Path
32 fixed SYN directives marcus.erlandsson 4927d 20h /versatile_fifo/
31 port map unneback 4998d 13h /versatile_fifo/
30 port map unneback 4998d 13h /versatile_fifo/
29 ACTEL syn define unneback 5006d 11h /versatile_fifo/
28 ACTEL async dual way FIFO unneback 5013d 20h /versatile_fifo/
27 initial commit, dual way simplex FIFO unneback 5014d 12h /versatile_fifo/
26 added ACTEL synthesis directive as define, +ACTEL unneback 5014d 12h /versatile_fifo/
25 DFF SR as separate logic unneback 5154d 07h /versatile_fifo/
24 updated fifo interfaces with re/rd and we/wr unneback 5154d 22h /versatile_fifo/
23 unneback 5157d 10h /versatile_fifo/
22 async fifo with multiple queues unneback 5157d 11h /versatile_fifo/
21 added DFF SR unneback 5171d 08h /versatile_fifo/
20 unneback 5171d 15h /versatile_fifo/
19 DFF with async clear and set for Altera cycloneIV unneback 5172d 21h /versatile_fifo/
18 ADDR and DATA width set to 8 resp 32 unneback 5173d 11h /versatile_fifo/
17 based on updated versatile counter unneback 5177d 10h /versatile_fifo/
16 changed power of two style unneback 5440d 20h /versatile_fifo/
15 doc updated
gray_counter_defines added
dual port RAM updated		 unneback 5444d 13h /versatile_fifo/
14 added PDF unneback 5488d 20h /versatile_fifo/
13 adr update unneback 5489d 22h /versatile_fifo/
12 no mux on dual port mem read unneback 5502d 15h /versatile_fifo/
11 name conflict
wptr1 changed to wptr1_cnt etc		 unneback 5502d 18h /versatile_fifo/
10 rptr2 unneback 5502d 19h /versatile_fifo/
9 unneback 5508d 15h /versatile_fifo/
8 unneback 5508d 15h /versatile_fifo/
7 unneback 5508d 15h /versatile_fifo/
6 unneback 5508d 18h /versatile_fifo/
5 async compare for fifo full and empty unneback 5508d 18h /versatile_fifo/
4 unneback 5508d 22h /versatile_fifo/
3 unneback 5508d 23h /versatile_fifo/

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