URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk/] - Rev 29

Rev	Log message	Author	Age	Path
29	ACTEL syn define	unneback	5021d 08h	/versatile_fifo/trunk/
28	ACTEL async dual way FIFO	unneback	5028d 17h	/versatile_fifo/trunk/
27	initial commit, dual way simplex FIFO	unneback	5029d 09h	/versatile_fifo/trunk/
26	added ACTEL synthesis directive as define, +ACTEL	unneback	5029d 09h	/versatile_fifo/trunk/
25	DFF SR as separate logic	unneback	5169d 05h	/versatile_fifo/trunk/
24	updated fifo interfaces with re/rd and we/wr	unneback	5169d 19h	/versatile_fifo/trunk/
23		unneback	5172d 07h	/versatile_fifo/trunk/
22	async fifo with multiple queues	unneback	5172d 08h	/versatile_fifo/trunk/
21	added DFF SR	unneback	5186d 06h	/versatile_fifo/trunk/
20		unneback	5186d 13h	/versatile_fifo/trunk/
19	DFF with async clear and set for Altera cycloneIV	unneback	5187d 19h	/versatile_fifo/trunk/
18	ADDR and DATA width set to 8 resp 32	unneback	5188d 09h	/versatile_fifo/trunk/
17	based on updated versatile counter	unneback	5192d 07h	/versatile_fifo/trunk/
16	changed power of two style	unneback	5455d 17h	/versatile_fifo/trunk/
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5459d 11h	/versatile_fifo/trunk/
14	added PDF	unneback	5503d 17h	/versatile_fifo/trunk/
13	adr update	unneback	5504d 19h	/versatile_fifo/trunk/
12	no mux on dual port mem read	unneback	5517d 13h	/versatile_fifo/trunk/
11	name conflict wptr1 changed to wptr1_cnt etc	unneback	5517d 15h	/versatile_fifo/trunk/
10	rptr2	unneback	5517d 17h	/versatile_fifo/trunk/