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[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_dc_dw.v] - Rev 17

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17 based on updated versatile counter unneback 5193d 08h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5460d 11h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
12 no mux on dual port mem read unneback 5518d 13h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
8 unneback 5524d 13h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
7 unneback 5524d 13h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
4 unneback 5524d 20h /versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v

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