URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk/] [rtl/] [verilog/] [versatile_fifo_dual_port_ram_sc_dw.v] - Rev 32

Rev	Log message	Author	Age	Path
32	fixed SYN directives	marcus.erlandsson	4932d 15h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
26	added ACTEL synthesis directive as define, +ACTEL	unneback	5019d 06h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
18	ADDR and DATA width set to 8 resp 32	unneback	5178d 06h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
17	based on updated versatile counter	unneback	5182d 05h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5449d 08h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
12	no mux on dual port mem read	unneback	5507d 10h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v
4		unneback	5513d 17h	/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_sc_dw.v