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Rev Log message Author Age Path
28 added sync simplex FIFO unneback 4880d 21h /
27 added sync simplex FIFO unneback 4880d 21h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4880d 22h /
25 added sync FIFO unneback 4881d 12h /
24 added vl_dff_ce_set unneback 4882d 19h /
23 fixed port map error in async fifo 1r1w unneback 4883d 10h /
22 added binary counters unneback 4883d 15h /
21 reg -> wire in and or mux in logic unneback 4884d 11h /
20 naming convention vl_ unneback 4885d 22h /
19 naming convention vl_ unneback 4885d 22h /
18 naming convention vl_ unneback 4885d 23h /
17 unneback 4949d 12h /
16 converting utility for ROM unneback 4949d 23h /
15 added delay line unneback 4955d 20h /
14 reg -> wire for various signals unneback 4956d 01h /
13 cosmetic update unneback 4956d 02h /
12 added wishbone comliant modules unneback 4956d 22h /
11 async fifo simplex unneback 4957d 13h /
10 added dff_ce_clear unneback 4959d 12h /
9 added dff_ce_clear unneback 4959d 12h /
8 added dff_ce_clear unneback 4959d 12h /
7 mem update unneback 4959d 13h /
6 added library files unneback 4972d 13h /
5 memories added unneback 4972d 14h /
4 added counters unneback 4976d 17h /
3 various updates
counter added
unneback 4979d 13h /
2 initial check-in unneback 4980d 13h /
1 The project and the structure was created root 4985d 17h /

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