OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] - Rev 28

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 added sync simplex FIFO unneback 4055d 14h /
27 added sync simplex FIFO unneback 4055d 14h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4055d 15h /
25 added sync FIFO unneback 4056d 05h /
24 added vl_dff_ce_set unneback 4057d 12h /
23 fixed port map error in async fifo 1r1w unneback 4058d 03h /
22 added binary counters unneback 4058d 08h /
21 reg -> wire in and or mux in logic unneback 4059d 04h /
20 naming convention vl_ unneback 4060d 15h /
19 naming convention vl_ unneback 4060d 15h /
18 naming convention vl_ unneback 4060d 16h /
17 unneback 4124d 05h /
16 converting utility for ROM unneback 4124d 16h /
15 added delay line unneback 4130d 13h /
14 reg -> wire for various signals unneback 4130d 18h /
13 cosmetic update unneback 4130d 19h /
12 added wishbone comliant modules unneback 4131d 15h /
11 async fifo simplex unneback 4132d 06h /
10 added dff_ce_clear unneback 4134d 05h /
9 added dff_ce_clear unneback 4134d 05h /
8 added dff_ce_clear unneback 4134d 05h /
7 mem update unneback 4134d 06h /
6 added library files unneback 4147d 06h /
5 memories added unneback 4147d 07h /
4 added counters unneback 4151d 11h /
3 various updates
counter added
unneback 4154d 06h /
2 initial check-in unneback 4155d 06h /
1 The project and the structure was created root 4160d 10h /

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.