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Rev Log message Author Age Path
32 added vl_pll for ALTERA (cycloneIII) unneback 4415d 17h /
31 sync FIFO updated unneback 4435d 12h /
30 updated counter for level1 and level2 function unneback 4435d 13h /
29 updated counter for level1 and level2 function unneback 4435d 13h /
28 added sync simplex FIFO unneback 4436d 14h /
27 added sync simplex FIFO unneback 4436d 14h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4436d 15h /
25 added sync FIFO unneback 4437d 05h /
24 added vl_dff_ce_set unneback 4438d 12h /
23 fixed port map error in async fifo 1r1w unneback 4439d 03h /
22 added binary counters unneback 4439d 08h /
21 reg -> wire in and or mux in logic unneback 4440d 04h /
20 naming convention vl_ unneback 4441d 15h /
19 naming convention vl_ unneback 4441d 15h /
18 naming convention vl_ unneback 4441d 16h /
17 unneback 4505d 05h /
16 converting utility for ROM unneback 4505d 16h /
15 added delay line unneback 4511d 13h /
14 reg -> wire for various signals unneback 4511d 18h /
13 cosmetic update unneback 4511d 19h /

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