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Rev Log message Author Age Path
37 corrected polynom with length 20 unneback 4844d 01h /
36 added generic andor_mux unneback 4845d 09h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4845d 20h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4845d 21h /
33 updated wb3wb3_bridge unneback 4858d 23h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4866d 08h /
31 sync FIFO updated unneback 4886d 04h /
30 updated counter for level1 and level2 function unneback 4886d 04h /
29 updated counter for level1 and level2 function unneback 4886d 04h /
28 added sync simplex FIFO unneback 4887d 06h /
27 added sync simplex FIFO unneback 4887d 06h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4887d 07h /
25 added sync FIFO unneback 4887d 20h /
24 added vl_dff_ce_set unneback 4889d 04h /
23 fixed port map error in async fifo 1r1w unneback 4889d 19h /
22 added binary counters unneback 4890d 00h /
21 reg -> wire in and or mux in logic unneback 4890d 20h /
20 naming convention vl_ unneback 4892d 07h /
19 naming convention vl_ unneback 4892d 07h /
18 naming convention vl_ unneback 4892d 07h /
17 unneback 4955d 21h /
16 converting utility for ROM unneback 4956d 08h /
15 added delay line unneback 4962d 04h /
14 reg -> wire for various signals unneback 4962d 09h /
13 cosmetic update unneback 4962d 11h /
12 added wishbone comliant modules unneback 4963d 07h /
11 async fifo simplex unneback 4963d 22h /
10 added dff_ce_clear unneback 4965d 21h /
9 added dff_ce_clear unneback 4965d 21h /
8 added dff_ce_clear unneback 4965d 21h /

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