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Rev Log message Author Age Path
41 typo in registers.v unneback 4131d 01h /
40 new build environment with custom.v added as a result file unneback 4131d 01h /
39 added simple port prio based wb arbiter unneback 4131d 22h /
38 updated andor mux unneback 4131d 22h /
37 corrected polynom with length 20 unneback 4137d 19h /
36 added generic andor_mux unneback 4139d 03h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4139d 15h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4139d 15h /
33 updated wb3wb3_bridge unneback 4152d 17h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4160d 02h /
31 sync FIFO updated unneback 4179d 22h /
30 updated counter for level1 and level2 function unneback 4179d 22h /
29 updated counter for level1 and level2 function unneback 4179d 22h /
28 added sync simplex FIFO unneback 4181d 00h /
27 added sync simplex FIFO unneback 4181d 00h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4181d 01h /
25 added sync FIFO unneback 4181d 14h /
24 added vl_dff_ce_set unneback 4182d 22h /
23 fixed port map error in async fifo 1r1w unneback 4183d 13h /
22 added binary counters unneback 4183d 18h /
21 reg -> wire in and or mux in logic unneback 4184d 14h /
20 naming convention vl_ unneback 4186d 01h /
19 naming convention vl_ unneback 4186d 01h /
18 naming convention vl_ unneback 4186d 01h /
17 unneback 4249d 15h /
16 converting utility for ROM unneback 4250d 02h /
15 added delay line unneback 4255d 22h /
14 reg -> wire for various signals unneback 4256d 04h /
13 cosmetic update unneback 4256d 05h /
12 added wishbone comliant modules unneback 4257d 01h /

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