URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] - Rev 41

Rev	Log message	Author	Age	Path
41	typo in registers.v	unneback	4997d 05h	/
40	new build environment with custom.v added as a result file	unneback	4997d 05h	/
39	added simple port prio based wb arbiter	unneback	4998d 02h	/
38	updated andor mux	unneback	4998d 02h	/
37	corrected polynom with length 20	unneback	5003d 22h	/
36	added generic andor_mux	unneback	5005d 07h	/
35	added vl_mux2_andor and vl_mux3_andor localparam	unneback	5005d 18h	/
34	added vl_mux2_andor and vl_mux3_andor	unneback	5005d 18h	/
33	updated wb3wb3_bridge	unneback	5018d 20h	/
32	added vl_pll for ALTERA (cycloneIII)	unneback	5026d 06h	/
31	sync FIFO updated	unneback	5046d 02h	/
30	updated counter for level1 and level2 function	unneback	5046d 02h	/
29	updated counter for level1 and level2 function	unneback	5046d 02h	/
28	added sync simplex FIFO	unneback	5047d 03h	/
27	added sync simplex FIFO	unneback	5047d 03h	/
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	5047d 05h	/
25	added sync FIFO	unneback	5047d 18h	/
24	added vl_dff_ce_set	unneback	5049d 02h	/
23	fixed port map error in async fifo 1r1w	unneback	5049d 16h	/
22	added binary counters	unneback	5049d 22h	/
21	reg -> wire in and or mux in logic	unneback	5050d 18h	/
20	naming convention vl_	unneback	5052d 05h	/
19	naming convention vl_	unneback	5052d 05h	/
18	naming convention vl_	unneback	5052d 05h	/
17		unneback	5115d 18h	/
16	converting utility for ROM	unneback	5116d 05h	/
15	added delay line	unneback	5122d 02h	/
14	reg -> wire for various signals	unneback	5122d 07h	/
13	cosmetic update	unneback	5122d 09h	/
12	added wishbone comliant modules	unneback	5123d 05h	/