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Rev Log message Author Age Path
41 typo in registers.v unneback 3953d 07h /
40 new build environment with custom.v added as a result file unneback 3953d 07h /
39 added simple port prio based wb arbiter unneback 3954d 04h /
38 updated andor mux unneback 3954d 04h /
37 corrected polynom with length 20 unneback 3960d 00h /
36 added generic andor_mux unneback 3961d 09h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3961d 20h /
34 added vl_mux2_andor and vl_mux3_andor unneback 3961d 20h /
33 updated wb3wb3_bridge unneback 3974d 22h /
32 added vl_pll for ALTERA (cycloneIII) unneback 3982d 08h /
31 sync FIFO updated unneback 4002d 04h /
30 updated counter for level1 and level2 function unneback 4002d 04h /
29 updated counter for level1 and level2 function unneback 4002d 04h /
28 added sync simplex FIFO unneback 4003d 05h /
27 added sync simplex FIFO unneback 4003d 05h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4003d 07h /
25 added sync FIFO unneback 4003d 20h /
24 added vl_dff_ce_set unneback 4005d 04h /
23 fixed port map error in async fifo 1r1w unneback 4005d 18h /
22 added binary counters unneback 4006d 00h /
21 reg -> wire in and or mux in logic unneback 4006d 20h /
20 naming convention vl_ unneback 4008d 07h /
19 naming convention vl_ unneback 4008d 07h /
18 naming convention vl_ unneback 4008d 07h /
17 unneback 4071d 20h /
16 converting utility for ROM unneback 4072d 07h /
15 added delay line unneback 4078d 04h /
14 reg -> wire for various signals unneback 4078d 09h /
13 cosmetic update unneback 4078d 11h /
12 added wishbone comliant modules unneback 4079d 07h /

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