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Rev Log message Author Age Path
44 added target independet IO functionns unneback 4823d 09h /
43 added logic for parity generation and check unneback 4827d 13h /
42 updated mux_andor unneback 4831d 12h /
41 typo in registers.v unneback 4831d 14h /
40 new build environment with custom.v added as a result file unneback 4831d 14h /
39 added simple port prio based wb arbiter unneback 4832d 11h /
38 updated andor mux unneback 4832d 11h /
37 corrected polynom with length 20 unneback 4838d 08h /
36 added generic andor_mux unneback 4839d 16h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4840d 03h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4840d 03h /
33 updated wb3wb3_bridge unneback 4853d 05h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4860d 15h /
31 sync FIFO updated unneback 4880d 11h /
30 updated counter for level1 and level2 function unneback 4880d 11h /
29 updated counter for level1 and level2 function unneback 4880d 11h /
28 added sync simplex FIFO unneback 4881d 12h /
27 added sync simplex FIFO unneback 4881d 12h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4881d 14h /
25 added sync FIFO unneback 4882d 03h /
24 added vl_dff_ce_set unneback 4883d 11h /
23 fixed port map error in async fifo 1r1w unneback 4884d 02h /
22 added binary counters unneback 4884d 07h /
21 reg -> wire in and or mux in logic unneback 4885d 03h /
20 naming convention vl_ unneback 4886d 14h /
19 naming convention vl_ unneback 4886d 14h /
18 naming convention vl_ unneback 4886d 14h /
17 unneback 4950d 03h /
16 converting utility for ROM unneback 4950d 15h /
15 added delay line unneback 4956d 11h /

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